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ca13734bf0
Add kernel (Cortex-M0/M3/M4, Tricore, S32K, RISC-V ports), drivers, middleware (CAN stack, diagnostics, safety), applications, board support, build/test tooling, and documentation.
127 lines
4.2 KiB
C
127 lines
4.2 KiB
C
/**
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* @file stm32f4xx_config.h
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* @brief STM32F4 specific configuration
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*/
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#ifndef STM32F4XX_CONFIG_H
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#define STM32F4XX_CONFIG_H
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/* MCU Specific Definitions */
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#define STM32F407xx
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#define HSE_VALUE 8000000U /* External crystal */
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#define HSI_VALUE 16000000U /* Internal oscillator */
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#define LSE_VALUE 32768U /* Low speed external */
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#define LSI_VALUE 32000U /* Low speed internal */
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/* Clock Configuration */
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#define SYSTEM_CLOCK 168000000U /* 168 MHz */
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#define AHB_CLOCK 168000000U
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#define APB1_CLOCK 42000000U /* 42 MHz */
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#define APB2_CLOCK 84000000U /* 84 MHz */
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/* Peripheral Base Addresses */
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#define GPIOA_BASE 0x40020000U
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#define GPIOB_BASE 0x40020400U
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#define GPIOC_BASE 0x40020800U
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#define GPIOD_BASE 0x40020C00U
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#define GPIOE_BASE 0x40021000U
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#define GPIOF_BASE 0x40021400U
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#define GPIOG_BASE 0x40021800U
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#define GPIOH_BASE 0x40021C00U
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#define USART1_BASE 0x40011000U
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#define USART2_BASE 0x40004400U
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#define USART3_BASE 0x40004800U
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#define UART4_BASE 0x40004C00U
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#define UART5_BASE 0x40005000U
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#define USART6_BASE 0x40011400U
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#define SPI1_BASE 0x40013000U
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#define SPI2_BASE 0x40003800U
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#define SPI3_BASE 0x40003C00U
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#define I2C1_BASE 0x40005400U
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#define I2C2_BASE 0x40005800U
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#define I2C3_BASE 0x40005C00U
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#define ADC1_BASE 0x40012000U
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#define ADC2_BASE 0x40012100U
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#define ADC3_BASE 0x40012200U
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#define TIM1_BASE 0x40010000U
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#define TIM2_BASE 0x40000000U
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#define TIM3_BASE 0x40000400U
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#define TIM4_BASE 0x40000800U
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#define TIM5_BASE 0x40000C00U
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#define TIM8_BASE 0x40010400U
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#define TIM9_BASE 0x40014000U
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#define TIM10_BASE 0x40014400U
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#define TIM11_BASE 0x40014800U
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#define TIM12_BASE 0x40001800U
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#define TIM13_BASE 0x40001C00U
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#define TIM14_BASE 0x40002000U
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#define CAN1_BASE 0x40006400U
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#define CAN2_BASE 0x40006800U
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/* NVIC Priority Configuration */
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#define CAN1_IRQ_PRIORITY 5
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#define CAN2_IRQ_PRIORITY 5
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#define USART1_IRQ_PRIORITY 6
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#define USART2_IRQ_PRIORITY 6
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#define USART3_IRQ_PRIORITY 6
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#define SPI1_IRQ_PRIORITY 7
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#define SPI2_IRQ_PRIORITY 7
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#define I2C1_IRQ_PRIORITY 7
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#define I2C2_IRQ_PRIORITY 7
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#define ADC_IRQ_PRIORITY 8
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#define TIM_IRQ_PRIORITY 8
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/* DMA Configuration */
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#define DMA1_STREAM0_CHANNEL 0
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#define DMA1_STREAM1_CHANNEL 1
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#define DMA1_STREAM2_CHANNEL 2
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#define DMA1_STREAM3_CHANNEL 3
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#define DMA1_STREAM4_CHANNEL 4
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#define DMA1_STREAM5_CHANNEL 5
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#define DMA1_STREAM6_CHANNEL 6
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#define DMA1_STREAM7_CHANNEL 7
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#define DMA2_STREAM0_CHANNEL 0
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#define DMA2_STREAM1_CHANNEL 1
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#define DMA2_STREAM2_CHANNEL 2
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#define DMA2_STREAM3_CHANNEL 3
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#define DMA2_STREAM4_CHANNEL 4
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#define DMA2_STREAM5_CHANNEL 5
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#define DMA2_STREAM6_CHANNEL 6
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#define DMA2_STREAM7_CHANNEL 7
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/* GPIO Alternate Function Mapping */
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#define GPIO_AF_UART1_TX 7
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#define GPIO_AF_UART1_RX 7
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#define GPIO_AF_UART2_TX 7
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#define GPIO_AF_UART2_RX 7
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#define GPIO_AF_SPI1_SCK 5
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#define GPIO_AF_SPI1_MOSI 5
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#define GPIO_AF_SPI1_MISO 5
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#define GPIO_AF_I2C1_SCL 4
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#define GPIO_AF_I2C1_SDA 4
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#define GPIO_AF_CAN1_TX 9
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#define GPIO_AF_CAN1_RX 9
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#define GPIO_AF_TIM1_CH1 1
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#define GPIO_AF_TIM1_CH2 1
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#define GPIO_AF_TIM1_CH3 1
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#define GPIO_AF_TIM1_CH4 1
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/* Memory Configuration */
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#define FLASH_SIZE 0x100000U /* 1 MB */
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#define RAM_SIZE 0x20000U /* 128 KB */
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#define CCM_RAM_SIZE 0x10000U /* 64 KB */
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/* Safety Features */
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#define ENABLE_CLOCK_SECURITY_SYSTEM 1
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#define ENABLE_BROWN_OUT_RESET 1
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#define BROWNOUT_THRESHOLD 0x08 /* 2.7V */
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#endif /* STM32F4XX_CONFIG_H */
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