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Add full automotive RTOS project

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Add kernel (Cortex-M0/M3/M4, Tricore, S32K, RISC-V ports), drivers,
middleware (CAN stack, diagnostics, safety), applications, board
support, build/test tooling, and documentation.
This commit is contained in:
root
2026-08-23 03:35:29 -04:00
parent f113bf0a05
commit ca13734bf0
151 changed files with 23945 additions and 0 deletions
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drivers/mcu_specific/nxp_s32k/s32k14x_config.h
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/**
* @file s32k14x_config.h
* @brief NXP S32K14x specific configuration
*/
#ifndef S32K14X_CONFIG_H
#define S32K14X_CONFIG_H
/* MCU Specific Definitions */
#define S32K144
#define CPU_FREQUENCY 160000000U /* 160 MHz */
#define BUS_FREQUENCY 40000000U /* 40 MHz */
#define SLOW_FREQUENCY 10000000U /* 10 MHz */
/* Peripheral Base Addresses */
#define GPIOA_BASE 0x400FF000U
#define GPIOB_BASE 0x400FF040U
#define GPIOC_BASE 0x400FF080U
#define GPIOD_BASE 0x400FF0C0U
#define GPIOE_BASE 0x400FF100U
#define LPUART0_BASE 0x4006A000U
#define LPUART1_BASE 0x4006B000U
#define LPUART2_BASE 0x4006C000U
#define LPSPI0_BASE 0x4002C000U
#define LPSPI1_BASE 0x4002D000U
#define LPSPI2_BASE 0x4002E000U
#define LPI2C0_BASE 0x40066000U
#define LPI2C1_BASE 0x40067000U
#define ADC0_BASE 0x4003B000U
#define ADC1_BASE 0x4003C000U
#define FTM0_BASE 0x40038000U
#define FTM1_BASE 0x40039000U
#define FTM2_BASE 0x4003A000U
#define FTM3_BASE 0x40026000U
#define FTM4_BASE 0x40027000U
#define FLEXCAN0_BASE 0x40024000U
#define FLEXCAN1_BASE 0x40025000U
#define FLEXCAN2_BASE 0x4002B000U
/* Clock Configuration */
#define SOSC_FREQUENCY 8000000U /* System oscillator */
#define SPLL_FREQUENCY 160000000U /* System PLL */
#define FIRC_FREQUENCY 48000000U /* Fast IRC */
#define SIRC_FREQUENCY 8000000U /* Slow IRC */
/* Peripheral Clock Configuration */
#define FLEXCAN0_CLOCK 40000000U /* 40 MHz */
#define FLEXCAN1_CLOCK 40000000U
#define LPUART0_CLOCK 40000000U
#define LPSPI0_CLOCK 40000000U
#define LPI2C0_CLOCK 40000000U
#define ADC0_CLOCK 40000000U
#define FTM0_CLOCK 40000000U
/* NVIC Priority Configuration */
#define FLEXCAN0_IRQ_PRIORITY 5
#define FLEXCAN1_IRQ_PRIORITY 5
#define LPUART0_IRQ_PRIORITY 6
#define LPUART1_IRQ_PRIORITY 6
#define LPSPI0_IRQ_PRIORITY 7
#define LPI2C0_IRQ_PRIORITY 7
#define ADC0_IRQ_PRIORITY 8
#define FTM0_IRQ_PRIORITY 8
/* DMA Configuration */
#define DMA_CHANNEL_COUNT 16
#define DMA_MUX_CHANNEL_COUNT 16
/* Safety Features */
#define ENABLE_CLOCK_MONITORING 1
#define ENABLE_MEMORY_PROTECTION 1
#define WATCHDOG_TIMEOUT_MS 100
/* Memory Configuration */
#define FLASH_SIZE 0x100000U /* 1 MB */
#define RAM_SIZE 0x20000U /* 128 KB */
#define EEPROM_SIZE 0x1000U /* 4 KB */
/* CAN FD Configuration */
#define CAN_FD_ENABLED 1
#define CAN_FD_MAX_PAYLOAD 64
#endif /* S32K14X_CONFIG_H */
drivers/mcu_specific/nxp_s32k/s32k14x_hal.c
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/**
* @file s32k14x_hal.c
* @brief NXP S32K14x Hardware Abstraction Layer
*/
#include "s32k14x_config.h"
#include "can_driver.h"
#include "uart_driver.h"
#include "spi_driver.h"
#include "i2c_driver.h"
#include "gpio_driver.h"
#include "adc_driver.h"
#include "pwm_driver.h"
#include "S32K144.h"
/* CAN HAL Implementation */
int hal_can_init(uint32_t baudrate, uint8_t frame_type, bool enable_fd) {
/* Enable FLEXCAN0 clock */
PCC->PCCn[PCC_FlexCAN0_INDEX] |= PCC_PCCn_CGC_MASK;
/* Configure CAN pins */
// PTE4 - CAN0_RX, PTE5 - CAN0_TX
PCC->PCCn[PCC_PORTE_INDEX] |= PCC_PCCn_CGC_MASK;
PORTE->PCR[4] = PORT_PCR_MUX(5); /* CAN0_RX */
PORTE->PCR[5] = PORT_PCR_MUX(5); /* CAN0_TX */
/* Reset FLEXCAN */
CAN0->MCR |= CAN_MCR_SOFTRST_MASK;
while (CAN0->MCR & CAN_MCR_SOFTRST_MASK);
/* Configure for CAN FD if enabled */
if (enable_fd) {
CAN0->MCR |= CAN_MCR_FDEN_MASK; /* Enable FD */
}
/* Set baudrate */
uint32_t prescaler = BUS_FREQUENCY / (baudrate * 10); /* 10 time quanta */
CAN0->CTRL1 = CAN_CTRL1_PRESDIV(prescaler - 1) |
CAN_CTRL1_PSEG1(3) |
CAN_CTRL1_PSEG2(2) |
CAN_CTRL1_PROPSEG(4);
/* Configure message buffers */
CAN0->RXMGMASK = 0x1FFFFFFF; /* Accept all IDs */
CAN0->RX14MASK = 0x1FFFFFFF;
CAN0->RX15MASK = 0x1FFFFFFF;
/* Enable interrupts */
CAN0->IMASK1 |= CAN_IMASK1_BUF31TO0M_MASK;
CAN0->MCR |= CAN_MCR_IRMQ_MASK; /* Individual RX masking */
/* Normal mode */
CAN0->MCR &= ~CAN_MCR_HALT_MASK;
while (CAN0->MCR & CAN_MCR_FRZACK_MASK);
return 0;
}
int hal_can_send_message(const CanMessage_t* message, uint32_t* mailbox) {
/* Find free message buffer */
*mailbox = 0;
while (*mailbox < 32) {
if ((CAN0->IFLAG1 & (1 << *mailbox)) != 0) {
break;
}
(*mailbox)++;
}
if (*mailbox >= 32) {
return -1;
}
/* Configure message buffer */
CAN0->RAMn[*mailbox * 4 + 1] = (message->id.id << 18) |
(message->id.is_extended ? 1 << 29 : 0) |
(message->length << 16);
/* Copy data */
for (int i = 0; i < message->length; i += 4) {
uint32_t data = 0;
for (int j = 0; j < 4 && (i + j) < message->length; j++) {
data |= (message->data[i + j] << (j * 8));
}
CAN0->RAMn[*mailbox * 4 + 2 + (i / 4)] = data;
}
/* Enable transmission */
CAN0->RAMn[*mailbox * 4] = CAN_WORD0_IDE_MASK |
CAN_WORD0_SRR_MASK |
CAN_WORD0_ESI_MASK |
CAN_WORD0_CODE(0xC); /* TX data */
return 0;
}
int hal_can_receive_message(CanMessage_t* message) {
/* Check for received messages */
uint32_t iflag = CAN0->IFLAG1;
if (iflag == 0) {
return -1;
}
/* Find received message buffer */
uint32_t mailbox = 0;
while (mailbox < 32) {
if (iflag & (1 << mailbox)) {
break;
}
mailbox++;
}
if (mailbox >= 32) {
return -1;
}
/* Read message */
uint32_t word0 = CAN0->RAMn[mailbox * 4];
uint32_t word1 = CAN0->RAMn[mailbox * 4 + 1];
/* Check if RX buffer */
if ((word0 & CAN_WORD0_CODE_MASK) != CAN_WORD0_CODE(0x4)) {
CAN0->IFLAG1 = (1 << mailbox); /* Clear flag */
return -1;
}
/* Get ID */
message->id.is_extended = (word0 & CAN_WORD0_IDE_MASK) != 0;
if (message->id.is_extended) {
message->id.id = (word0 & CAN_WORD0_ID_MASK) >> 0;
} else {
message->id.id = (word0 & CAN_WORD0_ID_MASK) >> 18;
}
/* Get data length */
message->length = (word1 & CAN_WORD1_DLC_MASK) >> 16;
/* Get data */
for (int i = 0; i < message->length; i += 4) {
uint32_t data = CAN0->RAMn[mailbox * 4 + 2 + (i / 4)];
for (int j = 0; j < 4 && (i + j) < message->length; j++) {
message->data[i + j] = (data >> (j * 8)) & 0xFF;
}
}
/* Clear flag */
CAN0->IFLAG1 = (1 << mailbox);
return 0;
}
/* GPIO HAL Implementation */
void hal_gpio_init(uint8_t port, uint8_t pin, GpioMode_t mode) {
GPIO_Type* gpio_port = get_gpio_port(port);
PORT_Type* port_config = get_port_config(port);
if (gpio_port == NULL || port_config == NULL) {
return;
}
/* Enable clock */
PCC->PCCn[PCC_PORTA_INDEX + port] |= PCC_PCCn_CGC_MASK;
PCC->PCCn[PCC_GPIOA_INDEX + port] |= PCC_PCCn_CGC_MASK;
/* Configure pin mux */
switch (mode) {
case GPIO_MODE_INPUT:
port_config->PCR[pin] = PORT_PCR_MUX(1);
gpio_port->PDDR &= ~(1 << pin);
break;
case GPIO_MODE_OUTPUT:
port_config->PCR[pin] = PORT_PCR_MUX(1);
gpio_port->PDDR |= (1 << pin);
break;
default:
break;
}
}
void hal_gpio_write(uint8_t port, uint8_t pin, bool value) {
GPIO_Type* gpio_port = get_gpio_port(port);
if (gpio_port == NULL) {
return;
}
if (value) {
gpio_port->PSOR = (1 << pin);
} else {
gpio_port->PCOR = (1 << pin);
}
}
bool hal_gpio_read(uint8_t port, uint8_t pin) {
GPIO_Type* gpio_port = get_gpio_port(port);
if (gpio_port == NULL) {
return false;
}
return (gpio_port->PDIR & (1 << pin)) != 0;
}
/* Helper functions */
static GPIO_Type* get_gpio_port(uint8_t port) {
switch (port) {
case 0: return PTA;
case 1: return PTB;
case 2: return PTC;
case 3: return PTD;
case 4: return PTE;
default: return NULL;
}
}
static PORT_Type* get_port_config(uint8_t port) {
switch (port) {
case 0: return PORTA;
case 1: return PORTB;
case 2: return PORTC;
case 3: return PORTD;
case 4: return PORTE;
default: return NULL;
}
}