ca13734bf0
Add kernel (Cortex-M0/M3/M4, Tricore, S32K, RISC-V ports), drivers, middleware (CAN stack, diagnostics, safety), applications, board support, build/test tooling, and documentation.
90 lines
2.8 KiB
C
90 lines
2.8 KiB
C
/**
|
|
* @file s32k14x_config.h
|
|
* @brief NXP S32K14x specific configuration
|
|
*/
|
|
|
|
#ifndef S32K14X_CONFIG_H
|
|
#define S32K14X_CONFIG_H
|
|
|
|
/* MCU Specific Definitions */
|
|
#define S32K144
|
|
#define CPU_FREQUENCY 160000000U /* 160 MHz */
|
|
#define BUS_FREQUENCY 40000000U /* 40 MHz */
|
|
#define SLOW_FREQUENCY 10000000U /* 10 MHz */
|
|
|
|
/* Peripheral Base Addresses */
|
|
#define GPIOA_BASE 0x400FF000U
|
|
#define GPIOB_BASE 0x400FF040U
|
|
#define GPIOC_BASE 0x400FF080U
|
|
#define GPIOD_BASE 0x400FF0C0U
|
|
#define GPIOE_BASE 0x400FF100U
|
|
|
|
#define LPUART0_BASE 0x4006A000U
|
|
#define LPUART1_BASE 0x4006B000U
|
|
#define LPUART2_BASE 0x4006C000U
|
|
|
|
#define LPSPI0_BASE 0x4002C000U
|
|
#define LPSPI1_BASE 0x4002D000U
|
|
#define LPSPI2_BASE 0x4002E000U
|
|
|
|
#define LPI2C0_BASE 0x40066000U
|
|
#define LPI2C1_BASE 0x40067000U
|
|
|
|
#define ADC0_BASE 0x4003B000U
|
|
#define ADC1_BASE 0x4003C000U
|
|
|
|
#define FTM0_BASE 0x40038000U
|
|
#define FTM1_BASE 0x40039000U
|
|
#define FTM2_BASE 0x4003A000U
|
|
#define FTM3_BASE 0x40026000U
|
|
#define FTM4_BASE 0x40027000U
|
|
|
|
#define FLEXCAN0_BASE 0x40024000U
|
|
#define FLEXCAN1_BASE 0x40025000U
|
|
#define FLEXCAN2_BASE 0x4002B000U
|
|
|
|
/* Clock Configuration */
|
|
#define SOSC_FREQUENCY 8000000U /* System oscillator */
|
|
#define SPLL_FREQUENCY 160000000U /* System PLL */
|
|
#define FIRC_FREQUENCY 48000000U /* Fast IRC */
|
|
#define SIRC_FREQUENCY 8000000U /* Slow IRC */
|
|
|
|
/* Peripheral Clock Configuration */
|
|
#define FLEXCAN0_CLOCK 40000000U /* 40 MHz */
|
|
#define FLEXCAN1_CLOCK 40000000U
|
|
#define LPUART0_CLOCK 40000000U
|
|
#define LPSPI0_CLOCK 40000000U
|
|
#define LPI2C0_CLOCK 40000000U
|
|
#define ADC0_CLOCK 40000000U
|
|
#define FTM0_CLOCK 40000000U
|
|
|
|
/* NVIC Priority Configuration */
|
|
#define FLEXCAN0_IRQ_PRIORITY 5
|
|
#define FLEXCAN1_IRQ_PRIORITY 5
|
|
#define LPUART0_IRQ_PRIORITY 6
|
|
#define LPUART1_IRQ_PRIORITY 6
|
|
#define LPSPI0_IRQ_PRIORITY 7
|
|
#define LPI2C0_IRQ_PRIORITY 7
|
|
#define ADC0_IRQ_PRIORITY 8
|
|
#define FTM0_IRQ_PRIORITY 8
|
|
|
|
/* DMA Configuration */
|
|
#define DMA_CHANNEL_COUNT 16
|
|
#define DMA_MUX_CHANNEL_COUNT 16
|
|
|
|
/* Safety Features */
|
|
#define ENABLE_CLOCK_MONITORING 1
|
|
#define ENABLE_MEMORY_PROTECTION 1
|
|
#define WATCHDOG_TIMEOUT_MS 100
|
|
|
|
/* Memory Configuration */
|
|
#define FLASH_SIZE 0x100000U /* 1 MB */
|
|
#define RAM_SIZE 0x20000U /* 128 KB */
|
|
#define EEPROM_SIZE 0x1000U /* 4 KB */
|
|
|
|
/* CAN FD Configuration */
|
|
#define CAN_FD_ENABLED 1
|
|
#define CAN_FD_MAX_PAYLOAD 64
|
|
|
|
#endif /* S32K14X_CONFIG_H */
|