root
ca13734bf0
Add kernel (Cortex-M0/M3/M4, Tricore, S32K, RISC-V ports), drivers, middleware (CAN stack, diagnostics, safety), applications, board support, build/test tooling, and documentation.
66 lines
1.8 KiB
C
66 lines
1.8 KiB
C
/**
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* @file portmacro.h
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* @brief ARM Cortex-M4 specific macros with FPU support
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*/
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#ifndef PORTMACRO_H
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#define PORTMACRO_H
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#include <stdint.h>
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#include "stm32f4xx.h" /* Adjust for specific MCU */
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/* Data Types */
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typedef uint32_t port_stack_type_t;
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typedef uint32_t port_base_type_t;
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/* Architecture Constants */
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#define PORT_STACK_GROWTH_DIRECTION (-1)
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#define PORT_BYTE_ALIGNMENT 8
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#define PORT_MAX_SYSCALL_INTERRUPT_PRIORITY 0x50
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/* Critical Section Macros */
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#define portENTER_CRITICAL() __asm volatile("CPSID I" ::: "memory")
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#define portEXIT_CRITICAL() __asm volatile("CPSIE I" ::: "memory")
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/* Interrupt Control */
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#define portENABLE_INTERRUPTS() __asm volatile("CPSIE I" ::: "memory")
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#define portDISABLE_INTERRUPTS() __asm volatile("CPSID I" ::: "memory")
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/* Context Switch */
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#define portYIELD() SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk
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#define portYIELD_FROM_ISR() SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk
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/* Memory Barriers */
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#define portMEMORY_BARRIER() __asm volatile("DMB" ::: "memory")
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#define portSYNC_BARRIER() __asm volatile("DSB" ::: "memory")
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#define portINSTRUCTION_BARRIER() __asm volatile("ISB" ::: "memory")
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/* NOP */
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#define portNOP() __asm volatile("NOP")
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/* FPU Control */
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#define portENABLE_FPU() \
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do { \
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SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); \
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__DSB(); \
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__ISB(); \
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} while(0)
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#define portDISABLE_FPU() \
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do { \
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SCB->CPACR &= ~((3UL << 10*2) | (3UL << 11*2)); \
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__DSB(); \
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__ISB(); \
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} while(0)
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/* Endian Definition */
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#define portBYTE_ORDER LITTLE_ENDIAN
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/* Optimization */
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#define portFORCE_INLINE __attribute__((always_inline)) inline
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/* Task Utilities */
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#define portTASK_RETURN_ADDRESS (0xFFFFFFFD)
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#endif /* PORTMACRO_H */
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