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ca13734bf0
Add kernel (Cortex-M0/M3/M4, Tricore, S32K, RISC-V ports), drivers, middleware (CAN stack, diagnostics, safety), applications, board support, build/test tooling, and documentation.
212 lines
6.6 KiB
C
212 lines
6.6 KiB
C
/**
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* @file memory_config.h
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* @brief Memory configuration for automotive RTOS
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*/
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#ifndef MEMORY_CONFIG_H
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#define MEMORY_CONFIG_H
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#include <stdint.h>
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/* ============================================================================
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* Memory Map Configuration
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* ============================================================================ */
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/* Flash memory configuration */
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#define FLASH_BASE_ADDRESS 0x08000000U
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#define FLASH_SIZE 0x00100000U /* 1 MB */
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#define FLASH_PAGE_SIZE 0x00002000U /* 8 KB */
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#define FLASH_SECTOR_SIZE 0x00010000U /* 64 KB */
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/* RAM memory configuration */
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#define RAM_BASE_ADDRESS 0x20000000U
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#define RAM_SIZE 0x00020000U /* 128 KB */
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/* CCM RAM (Core Coupled Memory) */
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#define CCM_RAM_BASE_ADDRESS 0x10000000U
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#define CCM_RAM_SIZE 0x00010000U /* 64 KB */
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/* External RAM configuration */
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#define EXT_RAM_BASE_ADDRESS 0x60000000U
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#define EXT_RAM_SIZE 0x00800000U /* 8 MB */
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/* ============================================================================
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* Memory Regions
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* ============================================================================ */
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/* Kernel memory region */
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#define KERNEL_MEMORY_START FLASH_BASE_ADDRESS
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#define KERNEL_MEMORY_SIZE 0x00040000U /* 256 KB */
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/* Application memory region */
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#define APP_MEMORY_START (KERNEL_MEMORY_START + KERNEL_MEMORY_SIZE)
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#define APP_MEMORY_SIZE 0x00080000U /* 512 KB */
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/* Calibration data region */
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#define CALIBRATION_MEMORY_START (APP_MEMORY_START + APP_MEMORY_SIZE)
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#define CALIBRATION_MEMORY_SIZE 0x00020000U /* 128 KB */
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/* Bootloader region */
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#define BOOTLOADER_MEMORY_START FLASH_BASE_ADDRESS
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#define BOOTLOADER_MEMORY_SIZE 0x00010000U /* 64 KB */
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/* ============================================================================
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* Stack Configuration
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* ============================================================================ */
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/* Main stack (MSP) */
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#define MAIN_STACK_SIZE 0x00001000U /* 4 KB */
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/* Process stack (PSP) */
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#define PROCESS_STACK_SIZE 0x00000800U /* 2 KB */
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/* ISR stack */
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#define ISR_STACK_SIZE 0x00000800U /* 2 KB */
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/* Exception stack */
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#define EXCEPTION_STACK_SIZE 0x00000400U /* 1 KB */
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/* ============================================================================
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* Heap Configuration
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* ============================================================================ */
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/* Heap region */
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#define HEAP_START (RAM_BASE_ADDRESS + 0x00010000U)
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#define HEAP_SIZE 0x00010000U /* 64 KB */
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/* Heap alignment */
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#define HEAP_ALIGNMENT 8
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/* Minimum heap block size */
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#define HEAP_MIN_BLOCK_SIZE 16
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/* Enable heap poisoning */
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#define ENABLE_HEAP_POISONING 1
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/* Heap poison value */
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#define HEAP_POISON_VALUE 0xDEADBEEF
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/* ============================================================================
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* Memory Protection Units (MPU)
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* ============================================================================ */
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/* Number of MPU regions */
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#define MPU_REGION_COUNT 8
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/* MPU region definitions */
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typedef struct {
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uint32_t base_address;
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uint32_t size;
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uint8_t permissions;
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bool executable;
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bool cacheable;
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bool bufferable;
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} MpuRegionConfig_t;
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/* Default MPU configuration */
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static const MpuRegionConfig_t mpu_regions[] = {
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/* Kernel code region (read-only, executable) */
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{
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.base_address = KERNEL_MEMORY_START,
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.size = KERNEL_MEMORY_SIZE,
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.permissions = 0x05, /* Read-only */
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.executable = true,
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.cacheable = true,
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.bufferable = false
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},
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/* Application code region (read-only, executable) */
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{
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.base_address = APP_MEMORY_START,
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.size = APP_MEMORY_SIZE,
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.permissions = 0x05, /* Read-only */
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.executable = true,
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.cacheable = true,
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.bufferable = false
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},
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/* RAM region (read-write, non-executable) */
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{
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.base_address = RAM_BASE_ADDRESS,
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.size = RAM_SIZE,
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.permissions = 0x03, /* Read-write */
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.executable = false,
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.cacheable = true,
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.bufferable = true
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},
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/* Peripheral region (read-write, non-executable) */
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{
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.base_address = 0x40000000U,
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.size = 0x10000000U, /* 256 MB */
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.permissions = 0x03, /* Read-write */
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.executable = false,
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.cacheable = false,
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.bufferable = true
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},
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/* External memory region */
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{
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.base_address = 0x60000000U,
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.size = 0x10000000U, /* 256 MB */
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.permissions = 0x03, /* Read-write */
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.executable = false,
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.cacheable = true,
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.bufferable = true
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}
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};
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#define MPU_REGION_COUNT_CONFIGURED (sizeof(mpu_regions) / sizeof(MpuRegionConfig_t))
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/* ============================================================================
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* Memory Pools
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* ============================================================================ */
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/* Memory pool configurations */
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#define MEMORY_POOL_COUNT 4
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typedef struct {
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uint32_t block_size;
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uint32_t block_count;
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uint32_t total_size;
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} MemoryPoolConfig_t;
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static const MemoryPoolConfig_t memory_pools[MEMORY_POOL_COUNT] = {
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{.block_size = 32, .block_count = 64, .total_size = 2048},
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{.block_size = 64, .block_count = 64, .total_size = 4096},
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{.block_size = 128, .block_count = 32, .total_size = 4096},
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{.block_size = 256, .block_count = 16, .total_size = 4096}
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};
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/* ============================================================================
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* DMA Configuration
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* ============================================================================ */
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/* DMA channels */
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#define DMA_CHANNEL_COUNT 8
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/* DMA buffer sizes */
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#define DMA_BUFFER_SIZE_CAN 512
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#define DMA_BUFFER_SIZE_UART 256
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#define DMA_BUFFER_SIZE_SPI 1024
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#define DMA_BUFFER_SIZE_ADC 512
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/* DMA priorities */
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#define DMA_PRIORITY_LOW 0
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#define DMA_PRIORITY_MEDIUM 1
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#define DMA_PRIORITY_HIGH 2
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#define DMA_PRIORITY_VERY_HIGH 3
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/* ============================================================================
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* ECC Configuration
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* ============================================================================ */
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/* Enable ECC */
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#define ENABLE_ECC 1
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/* ECC protected regions */
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#define ECC_FLASH_ENABLED 1
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#define ECC_RAM_ENABLED 1
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/* ECC error handling */
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#define ECC_SINGLE_ERROR_CORRECT 1
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#define ECC_DOUBLE_ERROR_DETECT 1
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#endif /* MEMORY_CONFIG_H */
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