RTOS/kernel/arch/arm/cortex-m4/port.c

/**
 * @file port.c
 * @brief ARM Cortex-M4 architecture specific port with FPU support
 * @note Cortex-M4 with FPU is common in modern automotive MCUs
 */

#include "kernel.h"
#include "task.h"
#include "scheduler.h"
#include "portmacro.h"

/* Context storage */
uint32_t* current_task_sp = NULL;
uint32_t* next_task_sp = NULL;

/* FPU context storage */
uint32_t current_fpu_context[32];
uint32_t next_fpu_context[32];

/* Exception priorities */
#define SYSTICK_PRIORITY    0xFF
#define PENDSV_PRIORITY     0xFF
#define SVC_PRIORITY        0x00

/* Initialize Architecture Port */
void port_init(void) {
    /* Set priority grouping - 4 bits preemption, 0 bits sub-priority */
    NVIC_SetPriorityGrouping(4);

    /* Enable FPU */
    SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2));

    /* Configure SysTick */
    SysTick->LOAD = (SystemCoreClock / 1000) - 1;
    SysTick->VAL = 0;
    SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
                    SysTick_CTRL_TICKINT_Msk |
                    SysTick_CTRL_ENABLE_Msk;

    /* Set exception priorities */
    NVIC_SetPriority(SysTick_IRQn, SYSTICK_PRIORITY);
    NVIC_SetPriority(PendSV_IRQn, PENDSV_PRIORITY);
    NVIC_SetPriority(SVCall_IRQn, SVC_PRIORITY);

    /* Enable faults */
    SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk |
                  SCB_SHCSR_BUSFAULTENA_Msk |
                  SCB_SHCSR_USGFAULTENA_Msk;

    /* Enable divide by zero trap */
    SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk;

    /* Enable unaligned access trap */
    SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
}

/* Start First Task */
void port_start_first_task(void) {
    TaskHandle_t first_task = scheduler_get_current_task();

    if (first_task == NULL) {
        return;
    }

    /* Restore FPU context if task uses FPU */
    if (first_task->context[31] & 0x10) {
        /* FPU was used - restore FPU registers */
        __asm volatile (
            "VLDM R0!, {S16-S31}\n"
            "VLDM R0!, {S0-S15}\n"
            :
            : "r" (first_task->context)
        );
    }

    /* Set PSP */
    __set_PSP((uint32_t)first_task->stack_pointer);

    /* Switch to PSP */
    __set_CONTROL(0x02);
    __ISB();

    /* Restore context */
    __asm volatile (
        "LDMIA R0!, {R4-R11}\n"
        "MSR PSP, R0\n"
        "MOV LR, #0xFFFFFFFD\n"
        "BX LR\n"
        :
        : "r" (first_task->stack_pointer)
    );
}

/* Context Switch */
void port_context_switch(uint32_t* current_context, uint32_t* next_context) {
    current_task_sp = current_context;
    next_task_sp = next_context;

    /* Trigger PendSV */
    SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;

    /* Data synchronization barrier */
    __DSB();
    __ISB();
}

/* Initialize Task Stack with FPU support */
uint32_t* port_initialize_task_stack(TaskFunction_t task_function,
                                     void* parameters,
                                     uint32_t* stack_top) {
    uint32_t* stack_ptr = stack_top;

    /* 8-byte alignment */
    stack_ptr = (uint32_t*)((uint32_t)stack_ptr & ~0x7);

    /* Exception frame with FPU */
    *(--stack_ptr) = 0x01000000;                    /* xPSR */
    *(--stack_ptr) = (uint32_t)task_function;        /* PC */
    *(--stack_ptr) = 0xFFFFFFFD;                     /* LR */
    *(--stack_ptr) = 0x00000000;                     /* R12 */
    *(--stack_ptr) = 0x00000003;                     /* R3 */
    *(--stack_ptr) = 0x00000002;                     /* R2 */
    *(--stack_ptr) = 0x00000001;                     /* R1 */
    *(--stack_ptr) = (uint32_t)parameters;           /* R0 */

    /* Additional context */
    *(--stack_ptr) = 0x0000000B;                     /* R11 */
    *(--stack_ptr) = 0x0000000A;                     /* R10 */
    *(--stack_ptr) = 0x00000009;                     /* R9 */
    *(--stack_ptr) = 0x00000008;                     /* R8 */
    *(--stack_ptr) = 0x00000007;                     /* R7 */
    *(--stack_ptr) = 0x00000006;                     /* R6 */
    *(--stack_ptr) = 0x00000005;                     /* R5 */
    *(--stack_ptr) = 0x00000004;                     /* R4 */

    /* FPU context (S0-S31) */
    for (int i = 0; i < 32; i++) {
        *(--stack_ptr) = 0;
    }

    /* FPSCR */
    *(--stack_ptr) = 0;

    return stack_ptr;
}

/* SysTick Handler */
void SysTick_Handler(void) {
    extern void kernel_tick_handler(void);
    kernel_tick_handler();
}

/* PendSV Handler with FPU context saving */
__attribute__((naked)) void PendSV_Handler(void) {
    __asm volatile (
        /* Check if FPU was used */
        "TST LR, #0x10\n"
        "IT EQ\n"
        "BEQ 1f\n"

        /* Save FPU context */
        "MRS R0, CONTROL\n"
        "TST R0, #0x04\n"
        "IT EQ\n"
        "BEQ 1f\n"

        /* Save FPU registers */
        "VSTMDB R0!, {S16-S31}\n"
        "VSTMDB R0!, {S0-S15}\n"

        "1:\n"
        /* Save core context */
        "MRS R0, PSP\n"
        "STMDB R0!, {R4-R11}\n"
        "LDR R1, =current_task_sp\n"
        "STR R0, [R1]\n"

        /* Load next context */
        "LDR R0, =next_task_sp\n"
        "LDR R1, [R0]\n"
        "LDMIA R1!, {R4-R11}\n"
        "MSR PSP, R1\n"

        /* Restore FPU context if needed */
        "TST LR, #0x10\n"
        "IT EQ\n"
        "BEQ 2f\n"

        /* Restore FPU registers */
        "VLDMIA R0!, {S0-S15}\n"
        "VLDMIA R0!, {S16-S31}\n"

        "2:\n"
        "BX LR\n"
    );
}

/* SVC Handler */
__attribute__((naked)) void SVC_Handler(void) {
    __asm volatile (
        "TST LR, #4\n"
        "ITE EQ\n"
        "MRSEQ R0, MSP\n"
        "MRSNE R0, PSP\n"
        "LDR R0, [R0, #24]\n"
        "LDRB R0, [R0, #-2]\n"
        "PUSH {LR}\n"
        "BL svc_handler\n"
        "POP {LR}\n"
        "BX LR\n"
    );
}

/* Fault Handlers */
void MemManage_Handler(void) {
    uint32_t fault_address = SCB->MMFAR;
    uint32_t fault_status = SCB->CFSR;

    extern void fault_handler_process(uint32_t type, uint32_t address, uint32_t status);
    fault_handler_process(2, fault_address, fault_status);

    while(1);
}

void BusFault_Handler(void) {
    uint32_t fault_address = SCB->BFAR;
    uint32_t fault_status = SCB->CFSR;

    extern void fault_handler_process(uint32_t type, uint32_t address, uint32_t status);
    fault_handler_process(3, fault_address, fault_status);

    while(1);
}

void UsageFault_Handler(void) {
    uint32_t fault_status = SCB->CFSR;

    extern void fault_handler_process(uint32_t type, uint32_t address, uint32_t status);
    fault_handler_process(4, 0, fault_status);

    while(1);
}

void HardFault_Handler(void) {
    uint32_t fault_status = SCB->HFSR;

    extern void fault_handler_process(uint32_t type, uint32_t address, uint32_t status);
    fault_handler_process(1, 0, fault_status);

    while(1);
}