/**
 * @file portmacro.h
 * @brief ARM Cortex-M0 specific macros
 */

#ifndef PORTMACRO_H
#define PORTMACRO_H

#include <stdint.h>

/* Data Types */
typedef uint32_t port_stack_type_t;
typedef uint32_t port_base_type_t;

/* Architecture Constants */
#define PORT_STACK_GROWTH_DIRECTION    (-1)
#define PORT_BYTE_ALIGNMENT            8
#define PORT_MAX_SYSCALL_INTERRUPT_PRIORITY  3

/* Critical Section Macros */
#define portENTER_CRITICAL()    __disable_irq()
#define portEXIT_CRITICAL()     __enable_irq()

/* Interrupt Control */
#define portENABLE_INTERRUPTS()  __enable_irq()
#define portDISABLE_INTERRUPTS() __disable_irq()

/* Context Switch */
#define portYIELD()             SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk
#define portYIELD_FROM_ISR()    SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk

/* Memory Barriers */
#define portMEMORY_BARRIER()    __asm volatile("DMB")
#define portSYNC_BARRIER()      __asm volatile("DSB")
#define portINSTRUCTION_BARRIER() __asm volatile("ISB")

/* NOP */
#define portNOP()               __asm volatile("NOP")

#endif /* PORTMACRO_H */