/**
 * @file portmacro.h
 * @brief ARM Cortex-M4 specific macros with FPU support
 */

#ifndef PORTMACRO_H
#define PORTMACRO_H

#include <stdint.h>
#include "stm32f4xx.h"  /* Adjust for specific MCU */

/* Data Types */
typedef uint32_t port_stack_type_t;
typedef uint32_t port_base_type_t;

/* Architecture Constants */
#define PORT_STACK_GROWTH_DIRECTION    (-1)
#define PORT_BYTE_ALIGNMENT            8
#define PORT_MAX_SYSCALL_INTERRUPT_PRIORITY  0x50

/* Critical Section Macros */
#define portENTER_CRITICAL()    __asm volatile("CPSID I" ::: "memory")
#define portEXIT_CRITICAL()     __asm volatile("CPSIE I" ::: "memory")

/* Interrupt Control */
#define portENABLE_INTERRUPTS()  __asm volatile("CPSIE I" ::: "memory")
#define portDISABLE_INTERRUPTS() __asm volatile("CPSID I" ::: "memory")

/* Context Switch */
#define portYIELD()             SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk
#define portYIELD_FROM_ISR()    SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk

/* Memory Barriers */
#define portMEMORY_BARRIER()    __asm volatile("DMB" ::: "memory")
#define portSYNC_BARRIER()      __asm volatile("DSB" ::: "memory")
#define portINSTRUCTION_BARRIER() __asm volatile("ISB" ::: "memory")

/* NOP */
#define portNOP()               __asm volatile("NOP")

/* FPU Control */
#define portENABLE_FPU()        \
    do { \
        SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); \
        __DSB(); \
        __ISB(); \
    } while(0)

#define portDISABLE_FPU()       \
    do { \
        SCB->CPACR &= ~((3UL << 10*2) | (3UL << 11*2)); \
        __DSB(); \
        __ISB(); \
    } while(0)

/* Endian Definition */
#define portBYTE_ORDER          LITTLE_ENDIAN

/* Optimization */
#define portFORCE_INLINE        __attribute__((always_inline)) inline

/* Task Utilities */
#define portTASK_RETURN_ADDRESS     (0xFFFFFFFD)

#endif /* PORTMACRO_H */