/**
 * @file memory_config.h
 * @brief Memory configuration for automotive RTOS
 */

#ifndef MEMORY_CONFIG_H
#define MEMORY_CONFIG_H

#include <stdint.h>

/* ============================================================================
 * Memory Map Configuration
 * ============================================================================ */

/* Flash memory configuration */
#define FLASH_BASE_ADDRESS          0x08000000U
#define FLASH_SIZE                  0x00100000U  /* 1 MB */
#define FLASH_PAGE_SIZE             0x00002000U  /* 8 KB */
#define FLASH_SECTOR_SIZE           0x00010000U  /* 64 KB */

/* RAM memory configuration */
#define RAM_BASE_ADDRESS            0x20000000U
#define RAM_SIZE                    0x00020000U  /* 128 KB */

/* CCM RAM (Core Coupled Memory) */
#define CCM_RAM_BASE_ADDRESS        0x10000000U
#define CCM_RAM_SIZE                0x00010000U  /* 64 KB */

/* External RAM configuration */
#define EXT_RAM_BASE_ADDRESS        0x60000000U
#define EXT_RAM_SIZE                0x00800000U  /* 8 MB */

/* ============================================================================
 * Memory Regions
 * ============================================================================ */

/* Kernel memory region */
#define KERNEL_MEMORY_START         FLASH_BASE_ADDRESS
#define KERNEL_MEMORY_SIZE          0x00040000U  /* 256 KB */

/* Application memory region */
#define APP_MEMORY_START            (KERNEL_MEMORY_START + KERNEL_MEMORY_SIZE)
#define APP_MEMORY_SIZE             0x00080000U  /* 512 KB */

/* Calibration data region */
#define CALIBRATION_MEMORY_START    (APP_MEMORY_START + APP_MEMORY_SIZE)
#define CALIBRATION_MEMORY_SIZE     0x00020000U  /* 128 KB */

/* Bootloader region */
#define BOOTLOADER_MEMORY_START     FLASH_BASE_ADDRESS
#define BOOTLOADER_MEMORY_SIZE      0x00010000U  /* 64 KB */

/* ============================================================================
 * Stack Configuration
 * ============================================================================ */

/* Main stack (MSP) */
#define MAIN_STACK_SIZE             0x00001000U  /* 4 KB */

/* Process stack (PSP) */
#define PROCESS_STACK_SIZE          0x00000800U  /* 2 KB */

/* ISR stack */
#define ISR_STACK_SIZE              0x00000800U  /* 2 KB */

/* Exception stack */
#define EXCEPTION_STACK_SIZE        0x00000400U  /* 1 KB */

/* ============================================================================
 * Heap Configuration
 * ============================================================================ */

/* Heap region */
#define HEAP_START                  (RAM_BASE_ADDRESS + 0x00010000U)
#define HEAP_SIZE                   0x00010000U  /* 64 KB */

/* Heap alignment */
#define HEAP_ALIGNMENT              8

/* Minimum heap block size */
#define HEAP_MIN_BLOCK_SIZE         16

/* Enable heap poisoning */
#define ENABLE_HEAP_POISONING       1

/* Heap poison value */
#define HEAP_POISON_VALUE           0xDEADBEEF

/* ============================================================================
 * Memory Protection Units (MPU)
 * ============================================================================ */

/* Number of MPU regions */
#define MPU_REGION_COUNT            8

/* MPU region definitions */
typedef struct {
    uint32_t base_address;
    uint32_t size;
    uint8_t permissions;
    bool executable;
    bool cacheable;
    bool bufferable;
} MpuRegionConfig_t;

/* Default MPU configuration */
static const MpuRegionConfig_t mpu_regions[] = {
    /* Kernel code region (read-only, executable) */
    {
        .base_address = KERNEL_MEMORY_START,
        .size = KERNEL_MEMORY_SIZE,
        .permissions = 0x05,  /* Read-only */
        .executable = true,
        .cacheable = true,
        .bufferable = false
    },
    /* Application code region (read-only, executable) */
    {
        .base_address = APP_MEMORY_START,
        .size = APP_MEMORY_SIZE,
        .permissions = 0x05,  /* Read-only */
        .executable = true,
        .cacheable = true,
        .bufferable = false
    },
    /* RAM region (read-write, non-executable) */
    {
        .base_address = RAM_BASE_ADDRESS,
        .size = RAM_SIZE,
        .permissions = 0x03,  /* Read-write */
        .executable = false,
        .cacheable = true,
        .bufferable = true
    },
    /* Peripheral region (read-write, non-executable) */
    {
        .base_address = 0x40000000U,
        .size = 0x10000000U,  /* 256 MB */
        .permissions = 0x03,  /* Read-write */
        .executable = false,
        .cacheable = false,
        .bufferable = true
    },
    /* External memory region */
    {
        .base_address = 0x60000000U,
        .size = 0x10000000U,  /* 256 MB */
        .permissions = 0x03,  /* Read-write */
        .executable = false,
        .cacheable = true,
        .bufferable = true
    }
};

#define MPU_REGION_COUNT_CONFIGURED  (sizeof(mpu_regions) / sizeof(MpuRegionConfig_t))

/* ============================================================================
 * Memory Pools
 * ============================================================================ */

/* Memory pool configurations */
#define MEMORY_POOL_COUNT           4

typedef struct {
    uint32_t block_size;
    uint32_t block_count;
    uint32_t total_size;
} MemoryPoolConfig_t;

static const MemoryPoolConfig_t memory_pools[MEMORY_POOL_COUNT] = {
    {.block_size = 32,   .block_count = 64,  .total_size = 2048},
    {.block_size = 64,   .block_count = 64,  .total_size = 4096},
    {.block_size = 128,  .block_count = 32,  .total_size = 4096},
    {.block_size = 256,  .block_count = 16,  .total_size = 4096}
};

/* ============================================================================
 * DMA Configuration
 * ============================================================================ */

/* DMA channels */
#define DMA_CHANNEL_COUNT           8

/* DMA buffer sizes */
#define DMA_BUFFER_SIZE_CAN         512
#define DMA_BUFFER_SIZE_UART        256
#define DMA_BUFFER_SIZE_SPI         1024
#define DMA_BUFFER_SIZE_ADC         512

/* DMA priorities */
#define DMA_PRIORITY_LOW            0
#define DMA_PRIORITY_MEDIUM         1
#define DMA_PRIORITY_HIGH           2
#define DMA_PRIORITY_VERY_HIGH      3

/* ============================================================================
 * ECC Configuration
 * ============================================================================ */

/* Enable ECC */
#define ENABLE_ECC                  1

/* ECC protected regions */
#define ECC_FLASH_ENABLED           1
#define ECC_RAM_ENABLED             1

/* ECC error handling */
#define ECC_SINGLE_ERROR_CORRECT    1
#define ECC_DOUBLE_ERROR_DETECT     1

#endif /* MEMORY_CONFIG_H */