Add full automotive RTOS project
Add kernel (Cortex-M0/M3/M4, Tricore, S32K, RISC-V ports), drivers, middleware (CAN stack, diagnostics, safety), applications, board support, build/test tooling, and documentation.
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/**
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* @file port.c
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* @brief RISC-V RV32 architecture specific port
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* @note RISC-V is emerging in automotive applications
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*/
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#include "kernel.h"
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#include "task.h"
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#include "scheduler.h"
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#include "portmacro.h"
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/* Context storage */
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uint32_t* current_task_sp = NULL;
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uint32_t* next_task_sp = NULL;
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/* Machine Timer registers */
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#define MTIME_ADDR 0x0200BFF8
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#define MTIMECMP_ADDR 0x02004000
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/* Initialize Architecture Port */
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void port_init(void) {
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/* Configure machine timer for 1ms interrupts */
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volatile uint32_t* mtime = (uint32_t*)MTIME_ADDR;
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volatile uint32_t* mtimecmp = (uint32_t*)MTIMECMP_ADDR;
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uint32_t current_time = *mtime;
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*mtimecmp = current_time + (SystemCoreClock / 1000);
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/* Enable machine timer interrupt */
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__asm volatile (
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"li t0, 0x80\n" /* Machine Timer Interrupt Enable */
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"csrs mie, t0\n"
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);
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/* Enable global interrupts */
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__asm volatile (
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"csrsi mstatus, 0x8\n" /* Machine Interrupt Enable */
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);
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}
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/* Start First Task */
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void port_start_first_task(void) {
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TaskHandle_t first_task = scheduler_get_current_task();
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if (first_task == NULL) {
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return;
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}
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/* Load task stack pointer */
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__asm volatile (
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"mv sp, %0\n"
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"ret\n"
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:
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: "r" (first_task->stack_pointer)
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);
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}
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/* Context Switch */
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void port_context_switch(uint32_t* current_context, uint32_t* next_context) {
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current_task_sp = current_context;
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next_task_sp = next_context;
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/* Trigger software interrupt */
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__asm volatile (
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"li t0, 0x8\n" /* Machine Software Interrupt */
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"csrs mip, t0\n"
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);
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}
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/* Initialize Task Stack */
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uint32_t* port_initialize_task_stack(TaskFunction_t task_function,
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void* parameters,
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uint32_t* stack_top) {
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uint32_t* stack_ptr = stack_top;
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/* Align to 16 bytes */
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stack_ptr = (uint32_t*)((uint32_t)stack_ptr & ~0xF);
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/* Initial stack frame */
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*(--stack_ptr) = (uint32_t)parameters; /* a0 */
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*(--stack_ptr) = 0; /* a1 */
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*(--stack_ptr) = 0; /* a2 */
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*(--stack_ptr) = 0; /* a3 */
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*(--stack_ptr) = 0; /* a4 */
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*(--stack_ptr) = 0; /* a5 */
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*(--stack_ptr) = 0; /* a6 */
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*(--stack_ptr) = 0; /* a7 */
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*(--stack_ptr) = (uint32_t)task_function; /* ra */
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*(--stack_ptr) = 0; /* t0 */
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*(--stack_ptr) = 0; /* t1 */
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*(--stack_ptr) = 0; /* t2 */
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*(--stack_ptr) = 0; /* t3 */
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*(--stack_ptr) = 0; /* t4 */
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*(--stack_ptr) = 0; /* t5 */
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*(--stack_ptr) = 0; /* t6 */
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*(--stack_ptr) = 0; /* s0 */
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*(--stack_ptr) = 0; /* s1 */
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*(--stack_ptr) = 0; /* s2 */
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*(--stack_ptr) = 0; /* s3 */
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*(--stack_ptr) = 0; /* s4 */
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*(--stack_ptr) = 0; /* s5 */
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*(--stack_ptr) = 0; /* s6 */
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*(--stack_ptr) = 0; /* s7 */
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*(--stack_ptr) = 0; /* s8 */
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*(--stack_ptr) = 0; /* s9 */
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*(--stack_ptr) = 0; /* s10 */
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*(--stack_ptr) = 0; /* s11 */
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*(--stack_ptr) = 0; /* gp */
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*(--stack_ptr) = 0; /* tp */
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/* mstatus */
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*(--stack_ptr) = 0x00001880; /* MPP = Machine mode */
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return stack_ptr;
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}
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/* Machine Timer Interrupt Handler */
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void machine_timer_interrupt_handler(void) {
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/* Clear interrupt */
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volatile uint32_t* mtimecmp = (uint32_t*)MTIMECMP_ADDR;
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volatile uint32_t* mtime = (uint32_t*)MTIME_ADDR;
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*mtimecmp = *mtime + (SystemCoreClock / 1000);
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/* Call kernel tick handler */
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extern void kernel_tick_handler(void);
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kernel_tick_handler();
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}
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/* Machine Software Interrupt Handler */
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void machine_software_interrupt_handler(void) {
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/* Clear interrupt */
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__asm volatile (
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"li t0, 0x8\n"
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"csrc mip, t0\n"
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);
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/* Perform context switch */
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__asm volatile (
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/* Save current context */
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"addi sp, sp, -128\n"
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"sw ra, 0(sp)\n"
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"sw t0, 4(sp)\n"
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"sw t1, 8(sp)\n"
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"sw t2, 12(sp)\n"
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"sw s0, 16(sp)\n"
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"sw s1, 20(sp)\n"
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"sw a0, 24(sp)\n"
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"sw a1, 28(sp)\n"
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"sw a2, 32(sp)\n"
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"sw a3, 36(sp)\n"
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"sw a4, 40(sp)\n"
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"sw a5, 44(sp)\n"
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"sw a6, 48(sp)\n"
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"sw a7, 52(sp)\n"
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"sw s2, 56(sp)\n"
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"sw s3, 60(sp)\n"
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"sw s4, 64(sp)\n"
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"sw s5, 68(sp)\n"
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"sw s6, 72(sp)\n"
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"sw s7, 76(sp)\n"
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"sw s8, 80(sp)\n"
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"sw s9, 84(sp)\n"
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"sw s10, 88(sp)\n"
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"sw s11, 92(sp)\n"
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"sw t3, 96(sp)\n"
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"sw t4, 100(sp)\n"
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"sw t5, 104(sp)\n"
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"sw t6, 108(sp)\n"
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"csrr t0, mstatus\n"
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"sw t0, 112(sp)\n"
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"csrr t0, mepc\n"
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"sw t0, 116(sp)\n"
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/* Save current stack pointer */
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"la t0, current_task_sp\n"
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"sw sp, 0(t0)\n"
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/* Load next stack pointer */
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"la t0, next_task_sp\n"
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"lw sp, 0(t0)\n"
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/* Restore next context */
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"lw ra, 0(sp)\n"
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"lw t0, 4(sp)\n"
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"lw t1, 8(sp)\n"
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"lw t2, 12(sp)\n"
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"lw s0, 16(sp)\n"
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"lw s1, 20(sp)\n"
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"lw a0, 24(sp)\n"
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"lw a1, 28(sp)\n"
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"lw a2, 32(sp)\n"
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"lw a3, 36(sp)\n"
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"lw a4, 40(sp)\n"
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"lw a5, 44(sp)\n"
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"lw a6, 48(sp)\n"
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"lw a7, 52(sp)\n"
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"lw s2, 56(sp)\n"
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"lw s3, 60(sp)\n"
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"lw s4, 64(sp)\n"
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"lw s5, 68(sp)\n"
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"lw s6, 72(sp)\n"
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"lw s7, 76(sp)\n"
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"lw s8, 80(sp)\n"
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"lw s9, 84(sp)\n"
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"lw s10, 88(sp)\n"
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"lw s11, 92(sp)\n"
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"lw t3, 96(sp)\n"
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"lw t4, 100(sp)\n"
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"lw t5, 104(sp)\n"
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"lw t6, 108(sp)\n"
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"lw t0, 112(sp)\n"
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"csrw mstatus, t0\n"
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"lw t0, 116(sp)\n"
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"csrw mepc, t0\n"
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"addi sp, sp, 128\n"
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/* Return from interrupt */
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"mret\n"
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);
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}
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/* Enter Critical Section */
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void port_disable_interrupts(void) {
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__asm volatile (
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"csrci mstatus, 0x8\n" /* Clear Machine Interrupt Enable */
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);
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}
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/* Exit Critical Section */
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void port_enable_interrupts(void) {
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__asm volatile (
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"csrsi mstatus, 0x8\n" /* Set Machine Interrupt Enable */
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);
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}
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@@ -0,0 +1,39 @@
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/**
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* @file portmacro.h
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* @brief RISC-V RV32 specific macros
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*/
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#ifndef PORTMACRO_H
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#define PORTMACRO_H
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#include <stdint.h>
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/* Data Types */
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typedef uint32_t port_stack_type_t;
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typedef uint32_t port_base_type_t;
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/* Architecture Constants */
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#define PORT_STACK_GROWTH_DIRECTION (-1)
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#define PORT_BYTE_ALIGNMENT 16
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/* Critical Section Macros */
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#define portENTER_CRITICAL() __asm volatile("csrci mstatus, 0x8")
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#define portEXIT_CRITICAL() __asm volatile("csrsi mstatus, 0x8")
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/* Interrupt Control */
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#define portENABLE_INTERRUPTS() __asm volatile("csrsi mstatus, 0x8")
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#define portDISABLE_INTERRUPTS() __asm volatile("csrci mstatus, 0x8")
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/* Context Switch */
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#define portYIELD() __asm volatile("li t0, 0x8\ncsrs mip, t0")
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#define portYIELD_FROM_ISR() __asm volatile("li t0, 0x8\ncsrs mip, t0")
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/* Memory Barriers */
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#define portMEMORY_BARRIER() __asm volatile("fence")
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#define portSYNC_BARRIER() __asm volatile("fence")
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#define portINSTRUCTION_BARRIER() __asm volatile("fence.i")
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/* NOP */
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#define portNOP() __asm volatile("nop")
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#endif /* PORTMACRO_H */
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