Add full automotive RTOS project
Add kernel (Cortex-M0/M3/M4, Tricore, S32K, RISC-V ports), drivers, middleware (CAN stack, diagnostics, safety), applications, board support, build/test tooling, and documentation.
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/**
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* @file port.c
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* @brief ARM Cortex-M3 architecture specific port
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* @note Cortex-M3 is widely used in automotive ECUs
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*/
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#include "kernel.h"
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#include "task.h"
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#include "scheduler.h"
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#include "portmacro.h"
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/* Context storage */
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uint32_t* current_task_sp = NULL;
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uint32_t* next_task_sp = NULL;
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/* Exception priorities */
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#define SYSTICK_PRIORITY 0xFF
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#define PENDSV_PRIORITY 0xFF
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#define SVC_PRIORITY 0x00
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/* Initialize Architecture Port */
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void port_init(void) {
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/* Set priority grouping - 4 bits preemption, 0 bits sub-priority */
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NVIC_SetPriorityGrouping(4);
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/* Configure SysTick */
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SysTick->LOAD = (SystemCoreClock / 1000) - 1;
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SysTick->VAL = 0;
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SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
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SysTick_CTRL_TICKINT_Msk |
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SysTick_CTRL_ENABLE_Msk;
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/* Set exception priorities */
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NVIC_SetPriority(SysTick_IRQn, SYSTICK_PRIORITY);
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NVIC_SetPriority(PendSV_IRQn, PENDSV_PRIORITY);
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NVIC_SetPriority(SVCall_IRQn, SVC_PRIORITY);
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/* Enable faults */
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SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk |
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SCB_SHCSR_BUSFAULTENA_Msk |
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SCB_SHCSR_USGFAULTENA_Msk;
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}
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/* Start First Task */
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void port_start_first_task(void) {
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TaskHandle_t first_task = scheduler_get_current_task();
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if (first_task == NULL) {
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return;
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}
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/* Set PSP */
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__set_PSP((uint32_t)first_task->stack_pointer);
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/* Switch to PSP */
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__set_CONTROL(0x02);
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__ISB();
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/* Restore context */
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__asm volatile (
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"LDMIA R0!, {R4-R11}\n"
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"MSR PSP, R0\n"
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"MOV LR, #0xFFFFFFFD\n"
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"BX LR\n"
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);
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}
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/* Context Switch */
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void port_context_switch(uint32_t* current_context, uint32_t* next_context) {
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current_task_sp = current_context;
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next_task_sp = next_context;
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/* Trigger PendSV */
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SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
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/* Data synchronization barrier */
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__DSB();
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__ISB();
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}
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/* Yield */
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void port_yield(void) {
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SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
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}
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/* Yield from ISR */
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void port_yield_from_isr(void) {
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SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
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}
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/* Enter Critical Section */
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void port_disable_interrupts(void) {
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__disable_irq();
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}
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/* Exit Critical Section */
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void port_enable_interrupts(void) {
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__enable_irq();
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}
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/* Get Current Exception Number */
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uint32_t port_get_current_exception(void) {
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return (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk) >> SCB_ICSR_VECTACTIVE_Pos;
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}
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/* Initialize Task Stack */
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uint32_t* port_initialize_task_stack(TaskFunction_t task_function,
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void* parameters,
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uint32_t* stack_top) {
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uint32_t* stack_ptr = stack_top;
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/* 8-byte alignment */
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stack_ptr = (uint32_t*)((uint32_t)stack_ptr & ~0x7);
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/* Exception frame */
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*(--stack_ptr) = 0x01000000; /* xPSR */
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*(--stack_ptr) = (uint32_t)task_function; /* PC */
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*(--stack_ptr) = 0xFFFFFFFD; /* LR */
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*(--stack_ptr) = 0x00000000; /* R12 */
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*(--stack_ptr) = 0x00000003; /* R3 */
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*(--stack_ptr) = 0x00000002; /* R2 */
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*(--stack_ptr) = 0x00000001; /* R1 */
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*(--stack_ptr) = (uint32_t)parameters; /* R0 */
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/* Additional context */
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*(--stack_ptr) = 0x0000000B; /* R11 */
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*(--stack_ptr) = 0x0000000A; /* R10 */
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*(--stack_ptr) = 0x00000009; /* R9 */
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*(--stack_ptr) = 0x00000008; /* R8 */
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*(--stack_ptr) = 0x00000007; /* R7 */
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*(--stack_ptr) = 0x00000006; /* R6 */
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*(--stack_ptr) = 0x00000005; /* R5 */
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*(--stack_ptr) = 0x00000004; /* R4 */
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return stack_ptr;
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}
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/* SysTick Handler */
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void SysTick_Handler(void) {
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extern void kernel_tick_handler(void);
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kernel_tick_handler();
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}
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/* PendSV Handler */
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__attribute__((naked)) void PendSV_Handler(void) {
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__asm volatile (
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"MRS R0, PSP\n"
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"STMDB R0!, {R4-R11}\n"
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"LDR R1, =current_task_sp\n"
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"STR R0, [R1]\n"
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"LDR R0, =next_task_sp\n"
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"LDR R1, [R0]\n"
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"LDMIA R1!, {R4-R11}\n"
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"MSR PSP, R1\n"
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"BX LR\n"
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);
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}
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/* SVC Handler */
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__attribute__((naked)) void SVC_Handler(void) {
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__asm volatile (
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"TST LR, #4\n"
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"ITE EQ\n"
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"MRSEQ R0, MSP\n"
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"MRSNE R0, PSP\n"
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"LDR R0, [R0, #24]\n"
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"LDRB R0, [R0, #-2]\n"
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"PUSH {LR}\n"
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"BL svc_handler\n"
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"POP {LR}\n"
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"BX LR\n"
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);
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}
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/* Memory Management Fault Handler */
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void MemManage_Handler(void) {
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uint32_t fault_address;
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uint32_t fault_status;
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fault_address = SCB->MMFAR;
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fault_status = SCB->CFSR;
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extern void fault_handler_process(uint32_t type, uint32_t address, uint32_t status);
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fault_handler_process(2, fault_address, fault_status);
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while(1);
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}
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/* Bus Fault Handler */
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void BusFault_Handler(void) {
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uint32_t fault_address;
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uint32_t fault_status;
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fault_address = SCB->BFAR;
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fault_status = SCB->CFSR;
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extern void fault_handler_process(uint32_t type, uint32_t address, uint32_t status);
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fault_handler_process(3, fault_address, fault_status);
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while(1);
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}
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/* Usage Fault Handler */
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void UsageFault_Handler(void) {
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uint32_t fault_status = SCB->CFSR;
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extern void fault_handler_process(uint32_t type, uint32_t address, uint32_t status);
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fault_handler_process(4, 0, fault_status);
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while(1);
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}
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/* Hard Fault Handler */
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void HardFault_Handler(void) {
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uint32_t fault_address = 0;
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uint32_t fault_status = SCB->HFSR;
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extern void fault_handler_process(uint32_t type, uint32_t address, uint32_t status);
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fault_handler_process(1, fault_address, fault_status);
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while(1);
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}
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@@ -0,0 +1,162 @@
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/**
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* @file port_asm.s
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* @brief ARM Cortex-M3 assembly routines
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*/
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.syntax unified
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.thumb
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.arch armv7-m
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.section .text
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/* Global symbols */
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.global current_task_sp
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.global next_task_sp
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.global port_context_switch
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.global port_start_first_task
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.global port_initialize_task_stack
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.global port_disable_interrupts
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.global port_enable_interrupts
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/* Variables */
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.section .bss
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.align 2
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current_task_sp: .word 0
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next_task_sp: .word 0
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.section .text
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.thumb_func
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/* Start First Task */
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port_start_first_task:
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/* Load task stack pointer */
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ldr r0, =next_task_sp
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ldr r1, [r0]
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/* Set PSP */
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msr PSP, r1
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/* Switch to PSP */
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mov r0, #2
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msr CONTROL, r0
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isb
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/* Restore context */
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ldmia r1!, {r4-r11}
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msr PSP, r1
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mov lr, #0xFFFFFFFD
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bx lr
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/* PendSV Handler */
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PendSV_Handler:
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/* Save context */
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mrs r0, PSP
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stmdb r0!, {r4-r11}
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ldr r1, =current_task_sp
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str r0, [r1]
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/* Load next context */
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ldr r0, =next_task_sp
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ldr r1, [r0]
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ldmia r1!, {r4-r11}
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msr PSP, r1
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bx lr
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/* SVC Handler */
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SVC_Handler:
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tst lr, #4
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ite eq
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mrseq r0, MSP
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mrsne r0, PSP
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ldr r0, [r0, #24]
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ldrb r0, [r0, #-2]
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push {lr}
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bl svc_handler
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pop {lr}
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bx lr
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/* Disable Interrupts */
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port_disable_interrupts:
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cpsid i
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bx lr
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/* Enable Interrupts */
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port_enable_interrupts:
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cpsie i
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bx lr
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/* Memory Management Fault */
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MemManage_Handler:
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/* Save context */
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mrs r0, PSP
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stmdb r0!, {r4-r11}
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/* Get fault information */
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ldr r1, =0xE000ED34 /* MMFAR */
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ldr r1, [r1]
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ldr r2, =0xE000ED28 /* CFSR */
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ldr r2, [r2]
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/* Call fault handler */
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movs r0, #2
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bl fault_handler_process
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/* Infinite loop */
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b .
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/* Bus Fault Handler */
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BusFault_Handler:
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/* Save context */
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mrs r0, PSP
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stmdb r0!, {r4-r11}
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/* Get fault information */
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ldr r1, =0xE000ED38 /* BFAR */
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ldr r1, [r1]
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ldr r2, =0xE000ED28 /* CFSR */
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ldr r2, [r2]
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/* Call fault handler */
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movs r0, #3
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bl fault_handler_process
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/* Infinite loop */
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b .
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/* Usage Fault Handler */
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UsageFault_Handler:
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/* Save context */
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mrs r0, PSP
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stmdb r0!, {r4-r11}
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/* Get fault status */
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ldr r2, =0xE000ED28 /* CFSR */
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ldr r2, [r2]
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/* Call fault handler */
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movs r0, #4
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movs r1, #0
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bl fault_handler_process
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/* Infinite loop */
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b .
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/* Hard Fault Handler */
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HardFault_Handler:
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/* Save context */
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mrs r0, PSP
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stmdb r0!, {r4-r11}
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/* Get fault status */
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ldr r2, =0xE000ED2C /* HFSR */
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ldr r2, [r2]
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/* Call fault handler */
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movs r0, #1
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movs r1, #0
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bl fault_handler_process
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/* Infinite loop */
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b .
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.end
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@@ -0,0 +1,43 @@
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/**
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* @file portmacro.h
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* @brief ARM Cortex-M3 specific macros
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*/
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#ifndef PORTMACRO_H
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#define PORTMACRO_H
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#include <stdint.h>
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/* Data Types */
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typedef uint32_t port_stack_type_t;
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typedef uint32_t port_base_type_t;
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/* Architecture Constants */
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#define PORT_STACK_GROWTH_DIRECTION (-1)
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#define PORT_BYTE_ALIGNMENT 8
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#define PORT_MAX_SYSCALL_INTERRUPT_PRIORITY 0x50
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/* Critical Section Macros */
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#define portENTER_CRITICAL() __asm volatile("CPSID I" ::: "memory")
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#define portEXIT_CRITICAL() __asm volatile("CPSIE I" ::: "memory")
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/* Interrupt Control */
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#define portENABLE_INTERRUPTS() __asm volatile("CPSIE I" ::: "memory")
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#define portDISABLE_INTERRUPTS() __asm volatile("CPSID I" ::: "memory")
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/* Context Switch */
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#define portYIELD() SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk
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#define portYIELD_FROM_ISR() SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk
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/* Memory Barriers */
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#define portMEMORY_BARRIER() __asm volatile("DMB" ::: "memory")
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#define portSYNC_BARRIER() __asm volatile("DSB" ::: "memory")
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#define portINSTRUCTION_BARRIER() __asm volatile("ISB" ::: "memory")
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/* NOP */
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#define portNOP() __asm volatile("NOP")
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/* Endian Definition */
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#define portBYTE_ORDER LITTLE_ENDIAN
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#endif /* PORTMACRO_H */
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