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Add full automotive RTOS project

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Add kernel (Cortex-M0/M3/M4, Tricore, S32K, RISC-V ports), drivers,
middleware (CAN stack, diagnostics, safety), applications, board
support, build/test tooling, and documentation.
This commit is contained in:
root
2026-08-23 03:35:29 -04:00
parent f113bf0a05
commit ca13734bf0
151 changed files with 23945 additions and 0 deletions
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drivers/mcu_specific/infineon_tricore/tc3xx_config.h
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/**
* @file tc3xx_config.h
* @brief Infineon TriCore TC3xx specific configuration
*/
#ifndef TC3XX_CONFIG_H
#define TC3XX_CONFIG_H
/* MCU Specific Definitions */
#define TC397
#define CPU_FREQUENCY 300000000U /* 300 MHz */
#define PERIPHERAL_FREQUENCY 150000000U /* 150 MHz */
#define STM_FREQUENCY 100000000U /* 100 MHz */
/* Peripheral Base Addresses */
#define CAN0_BASE 0xF0200000U
#define CAN1_BASE 0xF0210000U
#define CAN2_BASE 0xF0220000U
#define CAN3_BASE 0xF0230000U
#define ASCLIN0_BASE 0xF0000000U
#define ASCLIN1_BASE 0xF0000100U
#define ASCLIN2_BASE 0xF0000200U
#define ASCLIN3_BASE 0xF0000300U
#define QSPI0_BASE 0xF0001000U
#define QSPI1_BASE 0xF0001100U
#define QSPI2_BASE 0xF0001200U
#define QSPI3_BASE 0xF0001300U
#define I2C0_BASE 0xF0002000U
#define I2C1_BASE 0xF0002100U
#define VADC0_BASE 0xF0020000U
#define VADC1_BASE 0xF0020100U
#define GTM_BASE 0xF0100000U
#define GPT12_BASE 0xF0003000U
/* Interrupt Priorities */
#define CAN0_IRQ_PRIORITY 5
#define CAN1_IRQ_PRIORITY 5
#define ASCLIN0_IRQ_PRIORITY 6
#define QSPI0_IRQ_PRIORITY 7
#define I2C0_IRQ_PRIORITY 7
#define VADC0_IRQ_PRIORITY 8
#define GTM_IRQ_PRIORITY 8
/* DMA Configuration */
#define DMA_CHANNEL_COUNT 128
#define DMA_PRIORITY_HIGH 0
#define DMA_PRIORITY_MEDIUM 1
#define DMA_PRIORITY_LOW 2
/* Safety Features */
#define ENABLE_SAFETY_WATCHDOG 1
#define WATCHDOG_TIMEOUT_MS 100
#define ENABLE_ECC 1
#define ENABLE_MEMORY_PROTECTION 1
/* Memory Configuration */
#define FLASH_SIZE 0x800000U /* 8 MB */
#define RAM_SIZE 0x280000U /* 2.5 MB */
#define DSPR_SIZE 0x20000U /* 128 KB per CPU */
/* CAN FD Configuration */
#define CAN_FD_ENABLED 1
#define CAN_FD_MAX_PAYLOAD 64
#define CAN_TX_FIFO_SIZE 32
#define CAN_RX_FIFO_SIZE 64
#endif /* TC3XX_CONFIG_H */
drivers/mcu_specific/infineon_tricore/tc3xx_hal.c
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/**
* @file tc3xx_hal.c
* @brief Infineon TriCore TC3xx Hardware Abstraction Layer
*/
#include "tc3xx_config.h"
#include "can_driver.h"
#include "uart_driver.h"
#include "spi_driver.h"
#include "i2c_driver.h"
#include "gpio_driver.h"
#include "adc_driver.h"
#include "pwm_driver.h"
#include "Ifx_Types.h"
#include "IfxCan_Can.h"
#include "IfxAsclin_Asc.h"
#include "IfxQspi_SpiMaster.h"
#include "IfxI2c_I2c.h"
#include "IfxPort.h"
#include "IfxVadc_Adc.h"
#include "IfxGtm_Tom_PwmHl.h"
/* CAN HAL Implementation */
int hal_can_init(uint32_t baudrate, uint8_t frame_type, bool enable_fd) {
/* Create CAN module configuration */
IfxCan_Can_Config canConfig;
IfxCan_Can_initModuleConfig(&canConfig, &MODULE_CAN0);
/* Configure node */
canConfig.nodeConfig[0].baudRate.baudrate = baudrate;
canConfig.nodeConfig[0].frame.type = IfxCan_FrameType_receive;
if (enable_fd) {
canConfig.nodeConfig[0].frame.mode = IfxCan_FrameMode_fd;
}
/* Initialize CAN module */
IfxCan_Can_initModule(&g_canDriver, &canConfig);
/* Configure TX FIFO */
IfxCan_Can_initTxFifo(&g_canDriver, &g_canTxFifo);
/* Configure RX FIFO */
IfxCan_Can_initRxFifo(&g_canDriver, &g_canRxFifo);
/* Enable interrupts */
IfxCan_Can_enableInterrupt(&g_canDriver, IfxCan_Interrupt_messageStoredToDedicatedRxFifo);
return 0;
}
int hal_can_send_message(const CanMessage_t* message, uint32_t* mailbox) {
/* Create TX message */
IfxCan_Can_Message txMessage;
/* Set message ID */
txMessage.messageId = message->id.id;
txMessage.extendedFrame = message->id.is_extended;
/* Set data */
txMessage.dataLengthCode = message->length;
for (int i = 0; i < message->length; i++) {
txMessage.data[i] = message->data[i];
}
/* Send message */
if (IfxCan_Can_sendMessage(&g_canDriver, &txMessage, &txMessage.messageId)
!= IfxCan_Status_ok) {
return -1;
}
*mailbox = 0;
return 0;
}
int hal_can_receive_message(CanMessage_t* message) {
/* Create RX message */
IfxCan_Can_Message rxMessage;
/* Receive message */
if (IfxCan_Can_readMessage(&g_canDriver, &rxMessage, &rxMessage.messageId)
!= IfxCan_Status_ok) {
return -1;
}
/* Copy message data */
message->id.id = rxMessage.messageId;
message->id.is_extended = rxMessage.extendedFrame;
message->length = rxMessage.dataLengthCode;
for (int i = 0; i < message->length; i++) {
message->data[i] = rxMessage.data[i];
}
return 0;
}
/* GPIO HAL Implementation */
void hal_gpio_init(uint8_t port, uint8_t pin, GpioMode_t mode) {
/* Configure port pin */
IfxPort_setPinMode(&MODULE_P00, pin, IfxPort_Mode_outputPushPullGeneral);
}
void hal_gpio_write(uint8_t port, uint8_t pin, bool value) {
if (value) {
IfxPort_setPinHigh(&MODULE_P00, pin);
} else {
IfxPort_setPinLow(&MODULE_P00, pin);
}
}
bool hal_gpio_read(uint8_t port, uint8_t pin) {
return IfxPort_getPinState(&MODULE_P00, pin);
}
/* UART HAL Implementation */
int hal_uart_init(uint8_t instance, UartConfig_t* config) {
/* Create ASCLIN configuration */
IfxAsclin_Asc_Config ascConfig;
IfxAsclin_Asc_initModuleConfig(&ascConfig, &MODULE_ASCLIN0);
/* Configure baudrate */
ascConfig.baudrate.baudrate = config->baudrate;
/* Configure pins */
ascConfig.pins = &g_ascPins;
/* Initialize module */
IfxAsclin_Asc_initModule(&g_ascDriver, &ascConfig);
return 0;
}